От: D&R SoC NewsAlert [SoC-NewsAlert@design-reuse.com]
Отправлено: 5 октября 2004 г. 13:08
Кому: Michael Dolinsky
Тема: D&R SoC News Alert - October 5, 2004
DR SoC News Alert
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EETimes Network
October 5, 2004    


Welcome to issue of October 5, 2004 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

SPONSORED BY: TRUE CIRCUITS, INC.

True Circuits, Inc. offers a family of award-winning clock generator, deskew, low-bandwidth and spread-spectrum PLLs and DDR DLLs that spans nearly all performance points and features typically requested by ASIC and FPGA designers.
These high-quality, low-jitter, silicon-proven hard macros are available for immediate delivery in a range of frequencies, multiplication factors, sizes and functions in TSMC, UMC and Chartered processes from 0.25um to 90nm.
Call (650) 691-2500 or visit http://www.truecircuits.com/dr9.

USB 2.0 Host Core w/ AHB from LSI Logic
DDR DLLs on TSMC CLN90GOD & CLN90GT from True Circuits, Inc.
UDP/IP Transmitter/Receiver, a High Speed Ethernet Communication Core from RealFast Intellectual Property AB
LVDS Tranceiver on UMC 0.15um (L150-ASIC) from Virtual Silicon
DDR2 SDRAM Controller from Altera
3GP Multiplexer / Demultiplexer Software for Embedded Systems from sci-worx GmbH
SafeXcel IP Content Inspection Engine, IP for Content Inspection Hardware Acceleration from SafeNet
Wanted IPs :
  • I/O short and fat to optimise core area
  • SD Card CPRM IP
  • In-Depth: Making platform ASICs easier to use
    Realising the Full Potential of Multi-core Designs
    Designing USB into embedded systems
    Inside a hybrid verification model
    Embedded test speeds system verification
    Embedded platforms pose test challenge
    Zero bugs is the goal for every embedded task
    Extending validation another level
    Integration drives embedded software development and hardware debug
    Infrastructure IPs build ICs out well
    Independent Logic IP Provider Market to Experience a 14.3% CAGR Between 2003 and 2008
    VIP: It's Time to Grow Up (Synopsys)
    IP/SOC PRODUCTS
    CEVA Launches Mobile-Media - The First Fully Programmable Solution For Mobile-Multimedia Applications
    Actel's New ARINC 429 IP Core Reduces Cost and Simplifies Integration for Avionics Systems Designers
    New DSP Extension Enables Signal and Media Processing On the Industry-Standard MIPS Architecture
    ARM Neon Technology Fuels Consumer Electronics Growth With Next-Generation Mobile Multimedia Acceleration
    Sarnoff To Demo MPEG-4 CIF Video Codec For Cell Phones On ARM Platform At FSA Suppliers Expo
    RF Engines's HyperSpeed and HyperLength FFT Cores dramatically increase performance ranges of FFT
    Vesta Corporation Adds GZIP Accelerator RTL Core
    STRUCTURED ASIC
    LSI Logic Simplifies High-Speed Serial Interface Design with Expanded Rapidchip Xtreme Family of Platform ASICs
    DEALS
    Industry-Standard MIPS Architecture Adopted by NEC Electronics for Enhanced Single-Chip Solution
    Ridgetop Selected by C & D Technologies for Electronic Prognostics in DC to DC Converters
    BUSINESS
    ARM Holdings plc and Artisan Components, Inc. Announce That U.S. Government Has Granted Early Termination of Antitrust Waiting Period
    Agere Systems Announces Plans to Reduce Expenses, Reaffirms Fourth Fiscal Quarter Revenue Outlook
    DAFCA Receives $1.8 Million ATP Grant to Develop Reconfigurable Infrastructure Platform for System-on-Chip Electronics
    Renesas Technology to Take Over SuperH, Inc. CPU Core Business
    Adiabatic Logic, a company focused on creating and licensing intellectual property (IP) in the low power technology arena, gains US$900k DTI funding boost
    Temento Systems starts activities in Germany and announces the creation of its own office
    LEGAL
    Court Denies Samsung's Appeal of Sanctions
    Court Schedules Trial Date for MOSAID Patent Lawsuit Against Samsung
    PEOPLE
    Bernie Aronson Joins Kilopass Technology as President and COO
    TSMC Senior Vice President and Chief Information Officer Dr. Quincy Lin to Retire
    DESIGN SERVICES
    Qualcomm to Acquire Chip Design Company Spike Technologies
    EMBEDDED SYSTEMS
    Broadcom Announces Industry's First Gigahertz Quad-Core Broadband Processor, Raising the Bar in Chip Multiprocessing for Next Generation Embedded and High- Density Computing Systems
    Atmel Introduces New Media Processor to Enhance Media Playback Applications on Digital TVs and Projectors
    ARM and Trusted Logic Announce Evaluation Version of Security Software For Microsoft Windows CE 5.0
    Accelerated Technology Announces Enhanced Microtec Compiler Support for PowerPC Processor Family
    Mentor Graphics Enables Hardware/Software Co-Verification with StarCore Processor Models
    ARC Announces MQX Software Availability for Freescale Semiconductor's ColdFire Processors
    Freescale Discloses High-Performance Dual Core Processor Architecture
    NEC Electronics Unveils Industry's First Mobile Phone Application Processor with Parallel Processing Capabilities
    FOUNDRIES
    TSMC to see slow Q4 as foundry market declines
    FPGA/CPLD
    Cypress MicroSystems Powerful New PSoC Enhances Integrated Systems Control
    Xilinx And Mercury Computer Systems Demonstrate Interoperable Serial RapidIO Solutions On An ATCA Platform
    Xilinx RapidIO Solution Successfully Interoperates With Freescale PowerQUICC III Processor & Tundra RapidIO Switch
    Xilinx Delivers Breakthrough Design Tool For High Performance Signal Processing With New System Generator For DSP v6.3I
    EDA
    iRoC Technologies Introduces Free Web-based Tool for Soft Error Risk Assessment of Integrated Circuits
    Artisan and Cadence Collaborate to Optimize Low-Power Chip Design; New Library Views Support Next-Generation Low Power Devices
    ROHM Standardizes on CoWare ConvergenSC System-on-Chip Design Environment for Electronic System Level Design
    System level design is here, Synopsys CTO says

    SPONSORED BY: TEMENTO SYSTEMS

    Temento Systems, innovative provider of test, debug and verify solutions for FPGA and Hardware Platforms now offer two Edition of its DiaLite On-Chip Instrumentation tool. The new HDL Fault Finder IP included into the Power Edge Edition allows accurate monitoring and display of logic events contained into your HDL code. Designers have now the possibility to insert Watchpoints and Breakpoints on the instruments and into the code, and make it run concurrently to the instrumentation.

    Click here to know more about Temento






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